library ieee;
use ieee.std_logic_1164.all;

entity fullAdder is
	port (
		ina : in bit;
		inb : in bit;
		cin : in bit;
		sum, cout : out bit
	);
end entity fullAdder;

architecture DATAFLOW of fullAdder is
	
begin

	sum <= ina xor inb xor cin; 
	cout <= (ina and inb) or (cin and (ina xor inb));

end architecture DATAFLOW;

architecture STRUCTURAL of fullAdder is
	
	component xor2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component; 
	
	component and2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component;
	
	component or2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component; 
	
	for all : xor2 use entity work.XOR2;
	for all : and2 use entity work.AND2;
	for all : or2 use entity work.OR2;
	
	signal sigVec : bit_vector(4 downTo 0);
	
begin

	XOR0 : xor2  port map(ina, inb, sigVec(0));
	XOR1 : xor2  port map(sigVec(0), cin, sigVec(3));
	
	AND0 : and2  port map(sigVec(0), cin, sigVec(1));
	AND1 : and2 port map(ina, inb, sigVec(2));
	
	OR0 : or2 port map(sigVec(1), sigVec(2), sigVec(4)); 
	
	sum <= sigVec(3);
	cout <= sigVec(4);
	
end architecture STRUCTURAL;
